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Benavides Benítez, José Ignacio Author

Performance modeling of atomic additions on gpu scratchpad memory

  • Gomez-Luna J.
  • Gonzalez-Linares J.
  • Benavides Benitez J.
  • Guil Mata N.

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS - 14/10/2013

10.1109/tpds.2012.319

Cite count: 25 (Scopus)
  • SJR Quartile: Q1
  • JCR Impact Factor: 2.173 (2013)
  • CiteScore: 7.6 (2020)
  • SJR: 0.843 (2013
  • SNIP: 3.133 (2013
  • JCR 5-year Impact Factor: 2.182
  • JCR Categories: ENGINEERING, ELECTRICAL & ELECTRONIC
  • SJR Categories: Hardware and Architecture (Q1); Signal Processing (Q1); Computational Theory and Mathematics (Q2)
Open Access

Concurrent calculations on reconfigurable logic devices applied to the analysis of video images

  • Geninatti S.
  • Benavides Benítez J.
  • Hernández Calviño M.
  • Mata N.

International Journal of Reconfigurable Computing - 22/11/2010

10.1155/2010/962057

Cite count:
  • CiteScore: 2 (2020)
  • SJR Categories: Hardware and Architecture

This author has no books, chapters or theses.

Optimizing the physical implementation of a reconfigurable cache

  • Gil A.
  • Calvino M.
  • Latorre F.
  • Gomez E.
  • Benavides Benitez J.

2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012 - 1/12/2012

10.1109/reconfig.2012.6416768

Cite count: 2 (Scopus)
  • SJR Categories: Computer Science Applications
Open Access

SimARQ, an automatic repeat request simulator for teaching purposes

  • García-García C.
  • Gómez-Luna J.
  • Herruzo Gomez E.
  • Benavides Benitez J.

Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering - 6/9/2012

10.1007/978-3-642-32304-1_17

Cite count:
  • SJR Quartile: Q4
  • CiteScore: 0.7 (2020)
  • SJR: 0.169 (2012
  • SNIP: 0.387 (2012
  • SJR Categories: Computer Networks and Communications (Q4)

Reconfigurable cache implemented on an FPGA

  • Santana Gil A.
  • Benavides Benitez J.
  • Hernandez Calviño M.
  • Herruzo Gómez E.

Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010 - 1/12/2010

10.1109/reconfig.2010.26

Cite count: 9 (Scopus)
  • SJR Categories: Computational Theory and Mathematics; Hardware and Architecture

This author has no patents.

This author has no reports or other types of publications.

Scopus: 2

Scopus: 1

Web of Science: 0

Last data update: 11/19/24 9:28 PM
Next scheduled update: 11/23/24 3:00 AM